// Copyright (C) 1953-2023 NUDT
// Verilog module name - descriptor_ack 
// Version: V4.3.0.20230314
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:             
//             
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module descriptor_ack
(
        i_clk              ,
        i_rst_n            ,
                           
        iv_desp            ,
        i_desp_wr          ,
        
        ov_desp_network               ,
        o_desp_wr_network             ,
        i_desp_ack_network            ,
        
        ov_desp_host                  ,
        o_desp_wr_host                ,
        i_desp_ack_host
	   
);
// I/O
// clk & rst
input                  i_clk  ;
input                  i_rst_n;  
//tsntag & bufid input from host_port
input          [35:0]  iv_desp         ;
input                  i_desp_wr       ;
//tsntag & bufid output
output reg     [11:0]  ov_desp_network          ;
output reg             o_desp_wr_network        ;
input                  i_desp_ack_network       ;

output reg     [11:0]  ov_desp_host          ;
output reg             o_desp_wr_host        ;
input                  i_desp_ack_host       ;
//***************************************************
//          control bufid to input queue 
//***************************************************
reg            [1:0]   ack_state;
localparam  IDLE_S               = 2'd0,
            WAIT_NETWORK_ACK_S   = 2'd1,
			WAIT_HOST_ACK_S      = 2'd2;
always @(posedge i_clk or negedge i_rst_n) begin
    if(!i_rst_n) begin         
        ov_desp_network             <= 12'b0;
        o_desp_wr_network           <= 1'b0;
		
		ov_desp_host                <= 12'b0;
		o_desp_wr_host              <= 1'b0;
		
        ack_state           <= IDLE_S;
    end
    else begin
        case(ack_state)
            IDLE_S:begin
                if(i_desp_wr == 1'b1)begin
				    if(iv_desp[35:12] == {16'hff01,8'h05})begin
						ov_desp_host             <= iv_desp[11:0];
						o_desp_wr_host           <= 1'b1;
						  
						ack_state           <= WAIT_HOST_ACK_S;
                    end
                    else begin
						ov_desp_network             <= iv_desp[11:0];
						o_desp_wr_network           <= 1'b1;
						  
						ack_state           <= WAIT_NETWORK_ACK_S;
                    end					
                end               
                else begin
                    ov_desp_network             <= 12'b0;
                    o_desp_wr_network           <= 1'b0;
					
					ov_desp_host                <= 12'b0;
					o_desp_wr_host              <= 1'b0;					
                    ack_state           <= IDLE_S;
                end
            end
            WAIT_NETWORK_ACK_S:begin          
                if(i_desp_ack_network == 1'b1)begin
                    ov_desp_network             <= 12'b0;
                    o_desp_wr_network           <= 1'b0;                
                    ack_state           <= IDLE_S;
                end
                else begin
                    ack_state <= WAIT_NETWORK_ACK_S;
                end
            end
            WAIT_HOST_ACK_S:begin          
                if(i_desp_ack_host == 1'b1)begin
                    ov_desp_host             <= 12'b0;
                    o_desp_wr_host           <= 1'b0;                
                    ack_state           <= IDLE_S;
                end
                else begin
                    ack_state <= WAIT_HOST_ACK_S;
                end
            end 			
            default:begin
                ov_desp_network             <= 12'b0;
                o_desp_wr_network           <= 1'b0;
				
				ov_desp_host             <= 12'b0;
				o_desp_wr_host           <= 1'b0;  				
                ack_state           <= IDLE_S;              
            end
        endcase            
    end
end 
endmodule